All work

8-Bit CPU

A processor built from the parts up: ALU, registers, control unit, and memory, each one verified on its own before it went into the datapath.

  • VHDL
  • Intel Quartus II
  • RTL Simulation
RTL waveform simulation of the CPU in Intel Quartus II

Overview

The assignment was part of the EC3 2330 Digital Logic Design course, focusing on creating a working processor, with the constraint that none of it could come out of a library. Every combinational and sequential block had to be designed, coded, and checked on its own before it went into the datapath. Most of the work happened at the module level, and integration came last.

Architecture

Arithmetic Logic Unit
Add, subtract, bitwise AND/OR/XOR, and shift operations.
Registers
Small storage locations holding operands and intermediate results.
Control Unit
Decodes instructions and sequences the activity of every other block.
Memory
32 locations storing both data and instructions.
Supporting logic
Multiplexers, demultiplexers, decoders, encoders, comparators, counters, and timers integrated into the datapath.
Block diagram of the CPU architecture showing decoders, sequencers, and the datapath, with the control unit outlined in blue
The full architecture: decoders, sequencers, the datapath, and how they connect. The control unit is outlined in blue.

Build process

Design
Each component was modelled in Quartus, either in VHDL or by building the circuit directly.
Verification
Every module was exercised with testbenches and RTL simulation before it was trusted.
Integration
Verified modules were connected into the full datapath and control logic, then tested by running short programs that mixed arithmetic, logic, and memory operations.

Outcome

The processor runs short programs that mix arithmetic, logic, and memory access. Verifying each block on its own first mattered more than I expected. Almost every bug that turned up during integration was a wiring problem rather than a logic problem, and those are much faster to track down.

What I'd do differently

Self-checking testbenches, from the beginning. I read a lot of waveforms by eye on this project, which is slow and easy to get wrong, and I didn't notice how much time it was costing me until fairly late. I'd also lock the instruction encoding before starting the control unit. I changed it twice after the decoder was already built, and both times meant going back through it.